[ROCm][Perf] Enable gluon preshuffle path for DeepSeek-V3.2 sparse MLA (block_size=64)#41833
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…A (block_size=64) Both DeepseekV32IndexerBackend and ROCMAiterMLASparseBackend advertised [1, 64] from get_supported_kernel_block_sizes(). select_common_block_size picks the minimum, so the KV cache was always built with block_size=1. With block_size=1 the gluon preshuffle path added in vllm-project#41217 is never activated: Preshuffle=block_size==64 evaluates to False, the indexer Triton kernels use the NHD layout instead of SHUFFLE, and the decode falls back to the slower stage1+reduce_sum two-kernel pipeline. Fix: advertise [64] only (matching CUDA behaviour), so block_size=64 is selected and the full vllm-project#41217 optimisation fires: - deepgemm_fp8_paged_mqa_logits with Preshuffle=True, KVBlockSize=64 - SHUFFLE layout in indexer_k_quant_and_cache / cp_gather_indexer - pre-built paged_kv_indptr (ragged metadata built once in build()) Depends on: [ROCm][Bugfix] Fix DeepSeek-V3.2 TP4 sparse MLA with HIP graphs vllm-project#41760
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Summary
DeepseekV32IndexerBackendandROCMAiterMLASparseBackendboth advertise[1, 64]fromget_supported_kernel_block_sizes()(added by #41217).select_common_block_sizepicks the minimum, so the KV cache is always built withblock_size=1on ROCm.With
block_size=1the gluon preshuffle path introduced in #41217 is never activated:Preshuffle=block_size==64evaluates toFalsestage1+reduce_sumtwo-kernel pipelineFix: return
[64]only (matching CUDA behaviour). This makesselect_common_block_sizepick 64 and activates the full #41217 optimisation:deepgemm_fp8_paged_mqa_logitswithPreshuffle=True,KVBlockSize=64indexer_k_quant_and_cache/cp_gather_indexerpaged_kv_indptr(ragged metadata built once inbuild())Test plan